Field of the Invention
The present invention relates to a memory cell with a trench which is formed in a substrate. The trench is suitable for configuring a trench capacitor and a vertical transistor above the trench capacitor in the trench.
Memory components, such as DRAMs (dynamic random access memories) include a cell array and a driving peripheral area, with individual memory cells configured in the cell array.
A DRAM chip holds a matrix of memory cells which are configured in the form of rows and columns and are driven by word lines and bit lines. Data are read from the memory cells or data are written to the memory cells by activating suitable word lines and bit lines.
Normally, a DRAM memory cell contains a transistor connected to a capacitor. The transistor includes, amongst other things, two diffusion regions isolated from one another by a channel which is controlled by a gate. Depending on the direction of the flow of current, one diffusion region is called the drain region and the other diffusion region is called the source region.
One of the diffusion regions is connected to a bit line, the other diffusion region is connected to a capacitor, and the gate is connected to a word line. By applying suitable voltages to the gate, the transistor is controlled such that a flow of current between the diffusion regions through the channel is turned on and off.
The integration density is continuously increasing because of advancing miniaturization of memory components. The continuous increase in the integration density means that the area available for each memory cell is being reduced further and further.
In order to utilize the available area effectively, the resulting transistor can be formed above a trench capacitor as a vertical transistor in a trench. A memory cell of this generic type having a trench capacitor and a vertical transistor is described in issued U.S. Pat. No. 5,744,386. Further details relating to trench capacitors or transistors are described in issued U.S. Pat. Nos. 5,177,576; 5,937,296; 5,977,579 and 5,208,657. However, a problem with the known variants of memory cells is that of connecting the gate of the vertical transistor to a word line and of connecting the drain contact of the vertical transistor to a bit line. With advancing miniaturization, the demands on these two connections in terms of alignment accuracy will increase further.
It is accordingly an object of the invention to provide a memory cell and a method for producing the memory cell which overcomes the above-mentioned disadvantageous of the prior art apparatus and methods of this general type. In particular, it is an object of the invention to provide an improved memory cell having a trench and an epitaxially grown layer enables the production processes to have increased alignment tolerances.
With the foregoing and other objects in view there is provided, in accordance with the invention, a memory cell that includes: a substrate; a trench which has a bottom region, a middle region, a top region and an inner wall and is configured in the substrate; an insulating collar which is configured in the middle region on the inner wall of the trench; a dielectric layer which is configured at least in the bottom region of the trench; a conductive trench filling which at least partially fills the bottom region and the middle region of the trench; an epitaxially grown layer which is configured in the top region of the trench on the inner wall of the trench and on the conductive trench filling; and a second dielectric layer that is configured in the top region of the trench and above the epitaxially grown layer. The second dielectric layer has an internal opening formed therein.
In this case, the channel of the vertical transistor is formed in the epitaxially grown layer and is provided with a gate oxide. The gate material is situated on the gate oxide.
The advantage of the second dielectric layer is that it can be used to form the gate connection from the word line to the gate material of the vertical transistor in a self-aligned manner.
In this context, the second dielectric layer serves as a mask for etching free the gate material when connecting it to the word line. The advantage of this is that the only alignment tolerances which have to be observed are much greater, which affords the opportunity to advance the miniaturization process further.
Another advantage is that the trench can be designed to be wider than the contacts and wider than the word line in order to utilize the existing area more efficiently, since the etching process automatically exposes the internal opening in the second dielectric layer. This permits a lower level of safety precautions and a space-saving word line layout.
With the foregoing and other objects in view there is also provided, in accordance with the invention14. A method for producing a memory cell, which comprises: forming a trench in a substrate; forming the trench with an inner wall and with a bottom region, a middle region, and a top region; forming an insulating collar on the inner wall of the trench and in the middle region thereof; forming a dielectric layer at least in the bottom region of the trench; forming a conductive trench filling in the bottom region of the trench on the dielectric layer; forming the conductive trench filling to be at least partially disposed in the middle region of the trench and on the insulating collar; epitaxially growing a layer on the inner wall, in the top region of the trench, and on the conductive trench filling; while epitaxially growing the layer, forming a trench therein; filling the trench formed in the epitaxially grown layer with a gate material; and disposing a second dielectric layer with an internal opening formed therein in the top region of the trench formed in the substrate and above the epitaxially grown layer.
In accordance with an added feature of the invention, a third dielectric layer is configured on the epitaxially grown layer below the second dielectric layer. In this configuration, the third dielectric layer is a gate oxide. In this case, it is advantageous that the gate oxide is produced on the epitaxially grown layer and insulates the channel from a gate material. The opening in the second dielectric layer is in this case smaller than the diameter of the gate material.
In accordance with an additional feature of the invention, an insulating trench is configured such that it surrounds the memory cell and an adjacent memory cell, and an active region which is doped is formed between the memory cell and the adjacent memory cell. This configuration connects two adjacent memory cells to an active region, on which the bit line contact can later be formed.
In accordance with another feature of the invention, the channel region of the vertical transistor is not insulated, as would be the case in an SOI transistor (silicon on insulator). The bulk connection improves the control response of the vertical transistor, and it can be put into the off state again by a suitable gate voltage. In addition, the insulating trench has the task of insulating the memory cell and the adjacent memory cell from the other memory cells, which reduces and prevents leakage currents.
In accordance with a further feature of the invention, the epitaxially grown layer has a bottom doped region, which is connected to the conductive trench filling, and a top doped region, which is connected to the active region. The doped regions represent the source region and the drain region of the vertical transistor.
In accordance with a further added feature of the invention, a bit line runs via the active region and makes contact with the active region. In this case, part of the bit line is routed over the insulating trench, and part is routed via the active region, thus making contact with the latter. This configuration means that the bit line has a low line capacitance, which is particularly advantageous when a memory cell is being read, since the ratio of bit line capacitance to memory cell capacitance should be as small as possible for reading so that the charge stored in the memory cell is able to reverse the charge on the bit line. In addition, the bit line can be formed from a low-impedance material, which makes the memory cell fast.
In accordance with a further additional feature of the invention, the bit line is encapsulated in a dielectric sheath. The dielectric sheath can be used as a self-aligning etching mask when the contact hole for the gate connection is etched, and can thus improve the alignment tolerance of the memory cell.
In accordance with yet an added feature of the invention, a gate material is configured on the third dielectric layer and extends at least to the internal opening in the second dielectric layer. In addition, a gate connection is configured on the gate material and extends through the internal opening in the second dielectric layer and through a glass layer to a word line, which may be configured on the glass layer. This configuration ensures that the gate material is connected to a word line through the internal opening in the second dielectric layer. In addition, it is advantageously possible to form the gate connection in a self-aligned fashion.
In accordance with yet an additional feature of the invention, the word line runs above the bit line. This configuration permits a low coupling capacitance between the bit line and the word line, which becomes advantageously apparent as a result of low crosstalk from the word line to the bit line when a memory cell is read. In addition, this reduces the total bit line capacitance, which increases the speed of the memory cell and improves reading reliability.
In accordance with yet another feature of the invention, a circuit peripheral area has transistors with gate electrodes, and the gate electrodes are formed in one process step with the bit line. The combination of production steps in the circuit peripheral area, which contains the drive logic for the memory cell array, with production steps for layers and structures in the cell array allows the production costs for a memory to be reduced. It is therefore very effective to produce the gate electrodes of the transistors in the switching peripheral area in one step with the bit line in the cell array.
In accordance with a concomitant feature of the invention, further trenches are configured next to the trench in a predominantly hexagonal pattern. The advantage of this configuration is that the available surface can be utilized in optimum fashion, since a hexagonal configuration of the trenches represents the highest packing density in a two-dimensional configuration. This allows each individual trench to be configured such that its distance from its next adjacent trench is uniform.
Other features which are considered as characteristic for the invention are set forth in the appended claims.
Although the invention is illustrated and described herein as embodied in a memory cell with trench, and method for production thereof, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.